1. Field of the Invention
The invention relates to a phase locked loop (PLL) circuit, and in particular to a charge pump circuit in a phase locked loop circuit.
2. Description of the Related Art
In line with the great progress in semiconductor technology, the operating speed of contemporary computers is getting increasingly fast. However, higher operating frequency causes more power consumption. In order to reduce the unnecessary power consumption, it is designed to reduce the operating voltage of computers from 5V to 3.3V, then further to 2.5V, even to less than 2.0V. In coordination with the decrease of operating voltage, it is necessary to modify a great number of circuits, such as an oscillator for providing a clock signal. In a current computer system, there is simultaneously a variety of clock frequencies. Generally, a phase locked loop circuit is used to generate a number of clock signals with different proportional frequencies on with respect to a reference clock signal for the uses of a plurality of sub-systems. Moreover, a voltage control oscillator is a main factor to affect the performance of the phase locked loop circuit. And, the performance of the voltage control oscillator depends on its own long term jitter and short term jitter and the variation of a power supply voltage.
FIG. 1 is a block circuit diagram showing a conventional phase locked loop circuit. Referring to FIG. 1, a phase locked loop circuit includes a phase detector 10, a charge pump 12, a lowpass filter (LPF) 14 and a voltage control oscillator (VCO) 16. In general, the less the fluctuation of the input voltage signal of the voltage control oscillator 16, the less the jitter of the output voltage. As a result, the phase locked loop circuit can have an output voltage with a stable frequency. To minimize the fluctuation of the voltage signal input to the voltage control oscillator 16, it is necessary to make two current sources located in the charge pump 12 have the same current flow.
FIG. 2 is a circuit diagram showing the charge pump 12 of FIG. 1. Referring to FIG. 2, switches SW1, SW 1, SW2, SW 2 consist of transistors which all operate in a linear region. When each transistor is turned off from an on-state, charges stored on the drain must be released, causing charge injection. The less the charges stored on the drain, the less the effect of the charge injection. As a result, the control voltage of the VCO 16 almost remains unchanged. Since the SW 1 and SW 2 operate in the linear region, charges are accumulated in their channels between on-state and off-state thereof. Most charges stored around the drain can be released, resulting in an effect on the output voltage.
A current is mirrored into a transistor T2 and a current source 12 by a transistor Q. Therefore, if the voltage on a node P3 is equal to that on a node P4, it can make the current source 12 have the same current flow as the transistor T2. Assume that the voltage on the node P4 is at a certain constant value. If the voltage on the node P3 is larger than that on the P4, the current I1 is slightly larger than the current I2 as a result of channel modulation. Nevertheless, the voltage on a node P2 must be larger than the voltage on the node P4. Since the gate and the drain of the transistor T1 are electrically coupled to each other to form a diode, it makes the transistor T1 have a current flow different from the transistor T2 if the voltage of the node P2 is equal to the voltage of the node P4. In addition, since the current of a current source I3 is mirrored by the transistor T1, the current source I3 has the same current flow as the transistor T1. As a whole, the current flows of the current source I2 and current source I3 are different in value. Typically, the current source I3 has a larger current flow than the current source I2. If the difference of the current flows of the current sources I2, I3 is larger, the fluctuation of the voltage becomes much larger. As a result, the jitter of the output voltage of the voltage control oscillator 14 becomes more serious.
Moreover, since the transistors operating in the linear region can be considered as resistors, the voltage variation of the output points will affect the nodes P1, P4 so as to change the values of the I2 and I3.